1. Field of the Invention
The invention relates in general to a tenon-and-mortise packaging structure and a manufacturing method thereof, and more particularly to a packaging structure which achieves precise positioning of stacked package by a CIP package.
2. Description of the Related Art
With the rapid progress in electronic products, the integrated circuit (IC) has become an indispensible product in information age and has been widely used in electronic devices such as notebook computer, mobile phone, personal digital assistant (PDA) and digital camera. In terms of the chip package structure of an electronic product, the electronic product must not only have as many active elements as possible to meet the requirements of multi-function and high-speed and high-frequency operation but meet the requirements of lightweight, slimness and compactness.
Currently, many IC packages, such as flip chip package, quad flat package, ball grid array and chip in polymer (CIP) package, are provided to accommodate a large number of electronic elements in a limited package space. The flip chip package is formed with the die facing downward and coupled to the substrate via a solder. The quad flat package (QFP) is formed via supporting the package structure with a metallic wire frame and connecting with a circuit board via the leads on two surfaces or four edges. The ball grid array (BGA) is connected with a circuit board via a solder ball. According to the CIP package, super-thin chips are embedded in the build-up layers of a printed circuit board. Firstly, the chip is placed on the substrate. Next, a dielectric material is used to form a dielectric layer and the chip is embedded in the dielectric layer. Then, a plurality of metallic wires is fabricated on the dielectric material by the way of electroplating for electrically connecting the chip to the substrate. However, the problem in the manufacturing process of CIP package is the yield rate to be desided by uniformity of the dielectric layer. As the dielectric layer is formed via spin-coating and then bring about a micro-porous structure after exposure and developing process, the uniformity of the dielectric layer becomes very hard to control during the manufacturing process, hence affecting the yield rate of CIP package. Furthermore, on the part of a stacked package, a plurality of embedded chips is fixed with an adhesive so as to form a stacked package. However, after repeated heating cycling in the manufacturing process, the adhesive may be detached and come off. Besides, during the stacking process, the yield rate of the package will be affected if the substrates are not positioned precisely. Therefore, the invention provides a new type of semiconductor chip package structure and method thereof to resolve the above problems.